A plated solder-bump process used for the manufacture of high-reliability flip chips is described. Characterization work done to improve the process manufacturability and the resulting product reliability gains are reviewed. Two detailed studies of the thin-film deposition conditions and the Cu pedestal plating parameters are described. Recommendations implemented as a result of these studies have reduced the bump-interconnect-failure level from a defect rate of approximately 500 p.p.m. to <10 p.p.m. Excellent temperature cycling performance of assembled hybrids was obtained. The process has been used in high-volume production to manufacture ICs used in automobiles (under-hood application). In process capability has improved from a Cp<1 to Cp>1.5. This work highlights the need and the benefits of detailed characterization, which results in more robust manufacturing processes and eventually in more reliable product performance.
Reliability improvements in solder bump processing for flip chips
Zuverlässigkeitsverbesserung beim Bump-Löten für Flip-Chips
1990
10 Seiten, 11 Quellen
Conference paper
English
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