In this presentation, we provide a brief glimpse at preliminary single event test results taken from two years of testing of the Xilinx V5QV Field Programmable Gate Array (FPGA). This presentation includes an overview of test philosophy and implementation.
Independent Single Event Upset Testing of the Xilinx V5QV
Single Event Effects (SEE) Symposium and the Military and Aerospace Programmable Logic Devices (MAPLD) Workshop ; 2014 ; La Jolla, CA, United States
2014-05-19
Miscellaneous
No indication
English
Testing Electronic Devices for Single-Event Upset
NTRS | 1986
|Single event upset (SEU) testing at JPL
NTRS | 1987
|