In this presentation, we provide a brief glimpse at preliminary single event test results taken from two years of testing of the Xilinx V5QV Field Programmable Gate Array (FPGA). This presentation includes an overview of test philosophy and implementation.


    Access

    Access via TIB

    Check availability in my library


    Export, share and cite



    Title :

    Independent Single Event Upset Testing of the Xilinx V5QV


    Contributors:

    Conference:

    Single Event Effects (SEE) Symposium and the Military and Aerospace Programmable Logic Devices (MAPLD) Workshop ; 2014 ; La Jolla, CA, United States


    Publication date :

    2014-05-19


    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English




    Single event upset suspectibility testing of the Xilinx Virtex II FPGA

    Carmichael, C. / Swift, C. / Yui, G. | NTRS | 2002


    Independent Single Event Upset Testing of the Microsemi RTG4: Preliminary Data

    Berg, Melanie / Kim, Hak / Phan, Anthony et al. | NTRS | 2016


    Independent Single Event Upset Testing of the Microsemi RTG4: Preliminary Data

    Berg, Melanie / Kim, Hak / Phan, Anthony et al. | NTRS | 2016


    Testing Electronic Devices for Single-Event Upset

    Nichols, D. K. / Price, W. E. / Malone, C. J. | NTRS | 1986


    Single event upset (SEU) testing at JPL

    Coss, James R. | NTRS | 1987