Heavy ion testing of the Xilinx Virtex II was conducted on the configuration, block RAM and user flip flop cells to determine their static single-event upset susceptibility using LETs of 1.2 to 60 MeVcm^2/mg. A software program specifically designed to count errors in the FPGA was used to reveal L1/e, values (the LET at which the cross section is l/e times the saturation cross-section) and single-event functional-interrupt failures.


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    Title :

    Single event upset suspectibility testing of the Xilinx Virtex II FPGA


    Contributors:
    Carmichael, C. (author) / Swift, C. (author) / Yui, G. (author)


    Publication date :

    2002-01-01


    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English