A high speed parallel full adder is designed which can perform carry-free addition of two modified signed digit quaternary numbers. For digital implementation, the sign digit quaternary numbers are represented using 3-bit 2's complement notation. The adder truth table with possible schemes of the electronic and optical implementation are provided.<>


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    Title :

    Fast carry free adder design using QSD number system


    Contributors:
    Awwal, A.A.S. (author) / Ahmed, J.U. (author)


    Publication date :

    1993-01-01


    Size :

    303288 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English