A high speed parallel full adder is designed which can perform carry-free addition of two modified signed digit quaternary numbers. For digital implementation, the sign digit quaternary numbers are represented using 3-bit 2's complement notation. The adder truth table with possible schemes of the electronic and optical implementation are provided.<>
Fast carry free adder design using QSD number system
01.01.1993
303288 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch