A complex digital circuit has adder as a basic unit. Overall circuit performance will depend on the design of the basic adder circuit. So, if we reduce the delay of the basic adder unit then overall circuit delay will reduce thus speed of the overall circuitry gets increased. In this paper we have improved the delay of CIA (carry increment adder). The improvement is achieved by incorporating HCA (Han-Carlson adder) and KSA (Kogge-Stone adder) in the design of RCA and CLA.A synthesis study is done in terms of delay, power and area which is carried out for comparative analysis. Simulations and synthesis are done in Xilinx ISE 14.7 version and coding is done in Verilog HDL.


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    Titel :

    Design and Execution of Enhanced Carry Increment Adder using Han-Carlson and Kogge-Stone adder Technique : Han-Carlson and Kogge-Stone adder is used to increase speed of adder circuitry


    Beteiligte:
    Varshney, Neha (Autor:in) / Arya, Greeshma (Autor:in)


    Erscheinungsdatum :

    2019-06-01


    Format / Umfang :

    1787818 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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