An efficient carry-free addition and borrow-free subtraction of modified signed-digit trinary number scheme is presented which may be used for parallel computing application. A digital 2 bit prototype adder was designed and implemented using electrically programmable logic device (EPLD).<>


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    Title :

    Efficient electronic implementation of modified signed-digit trinary carry free adder


    Contributors:
    Hossain, M.M. (author) / Ahmed, J.U. (author) / Awwal, A.A.S. (author)


    Publication date :

    1993-01-01


    Size :

    277529 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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