The reversible Logic system will be effective in low power dissipation. For the optimization of power in VLSI design, number of researchers is using reversible logic regularly. In the VLSI design, the use of reversible logic has many advantages because of its high speed, and low power dissipation. This paper provides the design and comparative analysis of reversible full adder using Peres gate with conventional full adder circuits. During comparison it is found that 44% improvement in total thermal power dissipation over the conventional adder circuit. These reversible logic circuits are verified and simulated using Verilog coding, Intel Quartus Prime 20.1


    Access

    Check access

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    Design and Analysis of Low Power Full Adder using Reversible Logic


    Contributors:


    Publication date :

    2022-12-01


    Size :

    776161 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English




    A novel low power multilpier and full adder using hybrid CMOS logic

    Vani, A. Swetha / Lokesh, M. Ratna / Devi, B. Sowmya et al. | IEEE | 2017


    Design and Analysis of Multipliers using Hybrid Full Adder

    Dhanasekar, J. / Niranjana, M.Ishwarya | IEEE | 2023


    Design and Analysis of FinFET-based Carry Lookahead Adder using GDI logic

    Suresh, Sujit / Haasini, M Sai / Kaushal, Shelja | IEEE | 2024


    A Novel Design of a 4 Bit Reversible ALU using Kogge Stone Adder

    Swetha Potharla / Rajkumar R | BASE | 2017

    Free access