In recent trends most of the digital circuits are combinations of full adders and multipliers. In past many reported that adders, multipliers are suffered from the problems of voltage swing and high noise when operated at low voltage. Consequently new design methodologies are being implemented in which hybrid CMOS logic full adder is one of the proposed circuit having low power consumption, high speed and good driving capability. Hybrid logic style is a different logic design to implement full adder. For this we adopted XOR and XNOR gates. These gates are regulated for obtaining sum output with pass transistor UPLD. In this paper we implemented multiplier by using Hybrid CMOS logic full adder. This has accurate results, low voltage swing. Here simulation results are verified by using TANNER TOOLS V16.0.


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    Title :

    A novel low power multilpier and full adder using hybrid CMOS logic




    Publication date :

    2017-04-01


    Size :

    621764 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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