Placers which only consider wire-length minimization may produce irresolvable routing-congested placement solution for VLSI circuits. Placement with routability approach is more realistic with current large problems. Therefore, it is required to develop in early stage an effective routability driven global placement algorithm for modern mixed sized circuit. This paper introduce a new and modern routability driven global placer inspired by the resource allocation and patterns in the plants. We mimic the resource allocation technique of the plants to various parts of it, in VLSI circuit placement problem. We present routability driven global placement in two stages. First, selecting suitable nets to place based on strength of net. Second, finding suitable bins for higher order nets to gets place while avoiding congestion. Result shows that at early stage we can reduce the congestion and hence provide an incentive for the later stages- Detailed placement. We performed our experiment on ISPD 2011 benchmark circuits and compared our HPWL and overall congestion with ISPD’11 contestants, Ripple, mPL11, SimPLR.
Global Placement for Large-scale Mixed-size Design VLSI Circuits using Plant Model
2018-03-01
1589008 byte
Conference paper
Electronic Resource
English
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