This paper reports our latest implementation results of a fully unrolled LDPC decoder prototyped in 28 nm CMOS technology. The decoder achieves 1218 Gbps coded throughput and consumes a 5.49 mm2 chip area. The standard min-sum decoding algorithm with four-bit quantization, five unrolled iterations, (648,540) parity matrix, and a seven-stage pipeline is employed. Such implementation achieves a higher data rate than adaptive degeneration and finite-alphabet decoding algorithms, requires less silicon than the solutions mentioned above, and is fully compliant with the IEEE 802.11n WLAN standard.


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    Title :

    Ultra high speed 802.11n LDPC decoder with seven-stage pipeline in 28 nm CMOS


    Contributors:
    Lopacinski, L. (author) / Hasani, A. (author) / Panic, G. (author) / Maletic, N. (author) / Schrape, O. (author) / Gutierrez, J. (author) / Krstic, M. (author) / Grass, E. (author) / Kraemer, R. (author)


    Publication date :

    2022-06-01


    Size :

    819351 byte





    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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