Real-time collision detection between a vehicle and obstacles will be a key target for next-generation car electronics system. In the proposed collision detection VLSI processor, the matching operation is drastically accelerated by using a Content-Addressable Memory (CAM) which evaluates the magnitude relationships between an input word and all the stored words in parallel. A new obstacle representation based on a union of rectangular solids is also used to reduce the obstacle memory capacity, so that the collision detection can be performed only by parallel magnitude comparison. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speed based on the COordinate Rotation DIgital Computation (CORDIC) algorithms. The collision detection time becomes 5.2ms using 20 PEs and five CAMs with a 42-kbit capacity.


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    Title :

    A collision detection processor for intelligent vehicles


    Additional title:

    Ein Prozessor für ein Kollisionswarnsystem für Kraftfahrzeuge


    Contributors:
    Hariyama, M. (author) / Kameyama, M. (author)

    Published in:

    IEICE Transactions on Electronics ; E76-C , 12 ; 1804-1811


    Publication date :

    1993


    Size :

    8 Seiten, 18 Quellen



    Type of media :

    Article (Journal)


    Type of material :

    Print


    Language :

    English






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    A collision detection multiprocessor for intelligent vehicles using a high-density CAM

    Hariyama, M. / Hanyu, T. / Kameyama, M. | Tema Archive | 1994


    A Collision Detection Multiprocessor for Intelligent Vehicles Using a High-Density CAM

    Hariyama, M. / Hanyu, T. / Kameyama, M. et al. | British Library Conference Proceedings | 1994