Real-time collision detection between a vehicle and obstacles will be a key target for next-generation car electronics system. In the proposed collision detection VLSI processor, the matching operation is drastically accelerated by using a Content-Addressable Memory (CAM) which evaluates the magnitude relationships between an input word and all the stored words in parallel. A new obstacle representation based on a union of rectangular solids is also used to reduce the obstacle memory capacity, so that the collision detection can be performed only by parallel magnitude comparison. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speed based on the COordinate Rotation DIgital Computation (CORDIC) algorithms. The collision detection time becomes 5.2ms using 20 PEs and five CAMs with a 42-kbit capacity.


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    Titel :

    A collision detection processor for intelligent vehicles


    Weitere Titelangaben:

    Ein Prozessor für ein Kollisionswarnsystem für Kraftfahrzeuge


    Beteiligte:
    Hariyama, M. (Autor:in) / Kameyama, M. (Autor:in)

    Erschienen in:

    IEICE Transactions on Electronics ; E76-C , 12 ; 1804-1811


    Erscheinungsdatum :

    1993


    Format / Umfang :

    8 Seiten, 18 Quellen



    Medientyp :

    Aufsatz (Zeitschrift)


    Format :

    Print


    Sprache :

    Englisch






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