Efficient utilization of computing elements reduces size while preserving throughput. VLSI architecture is pipeline Reed-Solomon decoder for correction of errors and erasures. Uses transform circuit to compute syndrome polynomial. Erasure information enters decoder as binary sequence. Applied to variety of digital communications involving error-correcting RS codes.


    Access

    Access via TIB

    Check availability in my library


    Export, share and cite



    Title :

    Single-Chip VLSI Reed-Solomon Decoder


    Contributors:

    Published in:

    Publication date :

    1988-05-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English




    Modular VLSI Reed-Solomon Decoder

    Liu, K. Y. | NTRS | 1986


    Modular VLSI Reed-Solomon Decoder

    Hsu, In-Shek / Truong, Trieu-Kie | NTRS | 1991


    Systolic VLSI Reed-Solomon Decoder

    Shao, H. M. / Truong, T. K. / Deutsch, L. J. et al. | NTRS | 1986


    Single-Chip VLSI Reed-Solomon Encoder

    Truong, T. K. / Deutsch, L. J. / Reed, I. S. | NTRS | 1986


    Fast Reed-Solomon Decoder

    Liu, K. Y. | NTRS | 1986