Efficient utilization of computing elements reduces size while preserving throughput. VLSI architecture is pipeline Reed-Solomon decoder for correction of errors and erasures. Uses transform circuit to compute syndrome polynomial. Erasure information enters decoder as binary sequence. Applied to variety of digital communications involving error-correcting RS codes.
Single-Chip VLSI Reed-Solomon Decoder
NASA Tech Briefs ; 12 , 5
1988-05-01
Miscellaneous
No indication
English
Modular VLSI Reed-Solomon Decoder
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|NTRS | 1986
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