Decoder for digital communications provides high-speed, pipelined ReedSolomon (RS) error-correction decoding of data streams. Principal new feature of proposed decoder is modification of Euclid greatest-common-divisor algorithm to avoid need for time-consuming computations of inverse of certain Galois-field quantities. Decoder architecture suitable for implementation on very-large-scale integrated (VLSI) chips with negative-channel metaloxide/silicon circuitry.


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    Title :

    Systolic VLSI Reed-Solomon Decoder


    Contributors:
    Shao, H. M. (author) / Truong, T. K. (author) / Deutsch, L. J. (author) / Yuen, J. H. (author)

    Published in:

    Publication date :

    1986-01-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English




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