An adaptive LZW algorithm for compressing partial bitstreams of Virtex FPGAs was presented. The adaptations of algorithm were based on analysis of the three-level data regularity of the configuration bitstreams. Partial bitstreams were created through Xilinx module-based partial reconfiguration flow. The experiment demonstrated down to 43.69% compression ratio for partial bitstreams of several real-world applications.


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    Title :

    Partial Reconfiguration Bitstream Compression for Virtex FPGAs


    Contributors:
    Gu, Haiyun (author) / Chen, Shurong (author)


    Publication date :

    2008-05-01


    Size :

    308536 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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