Thanks to their flexibility, FPGAs are nowadays widely used to implement digital systems' prototypes and, more frequently, their final releases. Reconfiguration traditionally required an external controller to upload contents in the FPGA. Dynamic Partial Reconfiguration (DPR) opens new horizons in FPGAs' applications, providing many new utilization paradigms, as it enables an FPGA to reconfigure itself: no external controller is required since it can be included in the FPGA. However, DPR also introduces reliability issues related to errors in the partial reconfiguration bitstreams. FPGA manufacturers currently provide solutions that are not efficient. In this paper new DfD (Design for Dependability) techniques are proposed. Exploiting information density of configuration data, they improve the performance while providing the same reliability characteristics as the previous ones.
Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS
2013-01-01
Conference paper
Electronic Resource
English
DDC: | 629 |
Fault-Tolerant Manager Core for Dynamic Partial Reconfiguration in FPGAs
Springer Verlag | 2016
|Single event mitigation for Xilinx 7-series FPGAs
IEEE | 2018
|SEU mitigation testing of Xilinx Virtex II FPGAs
NTRS | 2003
|