An adaptive LZW algorithm for compressing partial bitstreams of Virtex FPGAs was presented. The adaptations of algorithm were based on analysis of the three-level data regularity of the configuration bitstreams. Partial bitstreams were created through Xilinx module-based partial reconfiguration flow. The experiment demonstrated down to 43.69% compression ratio for partial bitstreams of several real-world applications.


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    Titel :

    Partial Reconfiguration Bitstream Compression for Virtex FPGAs


    Beteiligte:
    Gu, Haiyun (Autor:in) / Chen, Shurong (Autor:in)


    Erscheinungsdatum :

    01.05.2008


    Format / Umfang :

    308536 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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