We report a gated-ReRAM synaptic devices-based strategy for on-chip supervised learning. A vacancy-driven compact model for gated-ReRAM is presented and corroborated with experimental results. A supervised learning architecture is proposed that allows the feedback to be provided via gate terminal of gated-ReRAM to update weights in a highly parallel manner.


    Access

    Check access

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    Gated-ReRAM Based Strategies for On-Chip Supervised Learning


    Contributors:


    Publication date :

    2019-07-01


    Size :

    2012647 byte





    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



    ReRAM-Based Intrinsically Secure Memory: A Feasibility Analysis

    Olexa, Nicholas / Jha, Rashmi / Mandal, Soumyajit et al. | IEEE | 2019


    Mit ReRAM und MRAM in eine schnellere Zukunft

    British Library Online Contents | 2013