We report a gated-ReRAM synaptic devices-based strategy for on-chip supervised learning. A vacancy-driven compact model for gated-ReRAM is presented and corroborated with experimental results. A supervised learning architecture is proposed that allows the feedback to be provided via gate terminal of gated-ReRAM to update weights in a highly parallel manner.


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    Titel :

    Gated-ReRAM Based Strategies for On-Chip Supervised Learning


    Beteiligte:
    Rush, Andrew J. (Autor:in) / Jones, Alexander (Autor:in) / Herrmann, Eric (Autor:in) / Jha, Rashmi (Autor:in)


    Erscheinungsdatum :

    01.07.2019


    Format / Umfang :

    2012647 byte





    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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