Simulation technique saves testing. Uses interactive version of SPICE (Simulation Program with Integrated Circuit Emphasis). Device and subcircuit models available in software used to construct macromodel for an integrated bipolar transistor. Time-dependent current generators placed inside transistor macromodel to simulate charge collection from ion track. Significant finding of experiments is standard design practice of reducing power in unaddressed bipolar RAM cell increases sensitivity of cell to single-event upsets.


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    Titel :

    Simulating Single-Event Upsets in Bipolar RAM's


    Beteiligte:

    Erschienen in:

    Erscheinungsdatum :

    1986-06-01



    Medientyp :

    Sonstige


    Format :

    Keine Angabe


    Sprache :

    Englisch


    Schlagwörter :


    Heavy-ion induced single event upsets in a bipolar logic device

    Kolasinski, W.A. / Koga, R. | Tema Archiv | 1983


    Single event upsets in space

    PETERSEN, E. | AIAA | 1983


    New Mode For Single-Event Upsets

    Zoutendyk, John A. / Smith, Lawrence S. / Soli, George A. et al. | NTRS | 1988



    Estimating Rates Of Single-Event Upsets

    Zoutendyk, John A. | NTRS | 1988