Simulation technique saves testing. Uses interactive version of SPICE (Simulation Program with Integrated Circuit Emphasis). Device and subcircuit models available in software used to construct macromodel for an integrated bipolar transistor. Time-dependent current generators placed inside transistor macromodel to simulate charge collection from ion track. Significant finding of experiments is standard design practice of reducing power in unaddressed bipolar RAM cell increases sensitivity of cell to single-event upsets.
Simulating Single-Event Upsets in Bipolar RAM's
NASA Tech Briefs ; 10 , 1
1986-06-01
Miscellaneous
No indication
English
Heavy-ion induced single event upsets in a bipolar logic device
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|Estimating Rates Of Single-Event Upsets
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