A method for a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating is described. The method includes generating a set of clocks. The method also includes routing a selected one of the set of clocks for frequency measurement through one or more clock routing subsystems. The method further includes adjusting a frequency of the selected clock after the selected clock is routed through the clock routing subsystems. The method also includes communicating a sideband signal to indicate the adjusted frequency of the selected clock.


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    Titel :

    CLOCK MONITORING SUBSYSTEM FOR SYSTEM-ON-CHIP SUPPORTING DYNAMIC CLOCK SCALING AND CLOCK GATING


    Beteiligte:
    BHAT VANAMALI (Autor:in) / PHADKE AMOD (Autor:in) / DENA SINA (Autor:in) / TIPTON MICHAEL (Autor:in) / ANEJA AMIT (Autor:in) / BHOYAR PRACHIN SHESHRAO (Autor:in)

    Erscheinungsdatum :

    15.05.2025


    Medientyp :

    Patent


    Format :

    Elektronische Ressource


    Sprache :

    Englisch


    Klassifikation :

    IPC:    G06F ELECTRIC DIGITAL DATA PROCESSING , Elektrische digitale Datenverarbeitung / B60W CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION , Gemeinsame Steuerung oder Regelung von Fahrzeug-Unteraggregaten verschiedenen Typs oder verschiedener Funktion



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