Three-terminal, double-stacked-gate field-effect transistor (FET), developed as analog memory element. Particularly suited for use as synapse with variable connection strength in electronic neural network. Provides programmable, nonvolatile resistive connection, somewhat in manner of porous-gate FET described in "Porous-Floating-Gate Field-Effect Transistor" (NPO-17532). Resembles commercial erasable programmable read-only memory (EPROM) device, except for thickness of layers of silicon dioxide electrically isolating gates. Either p-channel or n-channel device.
Stacked-Gate FET's For Analog Memory Elements
NASA Tech Briefs ; 15 , 7
1991-07-01
Miscellaneous
No indication
English
Sub-Quarter-Micrometer-like V-Gate Pseudomorphic Doped-Channel FET's
British Library Conference Proceedings | 2002
|Improved process control for VMOS FET's
NTRS | 1980
|FET's Perform Well At Cryogenic Temperatures
NTRS | 1992
|NTRS | 1980
|Magnetic Analog Random-Access Memory
NTRS | 1991
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