Report describes technique using fault simulator implemented entirely in hardware to generate and optimize test vectors for microprocessor. Hardware fault simulator approach reduces test time, while maintaining high reliability in detecting faults.


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    Title :

    Hardware Fault Simulator Generates Test Vectors For Complex IC's


    Contributors:
    Timoc, C. C. (author) / Hess, L. M. (author) / Stott, F. R. (author)

    Published in:

    Publication date :

    1984-11-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English




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