Network channels elements of data array from memory ports to processor ports using a hardware-generated binary control work. Depending on control work selected, data may be shifted in increments or transposed in each of three levels to reach appropriate processing ports. A similar arrangement with reversed wiring is used to return data from processing ports to respective memory modules. Selection gate used in network incorporates two AND gates feeding an OR gate. In some logic families the OR gate may be fabricated as a "wired OR".


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    Title :

    Improved Parallel-Access Alinement Network


    Contributors:

    Published in:

    Publication date :

    1982-11-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English





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