Network channels elements of data array from memory ports to processor ports using a hardware-generated binary control work. Depending on control work selected, data may be shifted in increments or transposed in each of three levels to reach appropriate processing ports. A similar arrangement with reversed wiring is used to return data from processing ports to respective memory modules. Selection gate used in network incorporates two AND gates feeding an OR gate. In some logic families the OR gate may be fabricated as a "wired OR".


    Zugriff

    Zugriff über TIB

    Verfügbarkeit in meiner Bibliothek prüfen


    Exportieren, teilen und zitieren



    Titel :

    Improved Parallel-Access Alinement Network


    Beteiligte:
    Barnes, G. H. (Autor:in)

    Erschienen in:

    Erscheinungsdatum :

    01.11.1982



    Medientyp :

    Sonstige


    Format :

    Keine Angabe


    Sprache :

    Englisch


    Schlagwörter :



    Optical alinement system

    Thomas, N. L. | NTRS | 1976


    Alinement tolerant Schlieren system

    Gunter, W. D., Jr. | NTRS | 1977


    Tube Alinement for Machining

    Garcia, J. | NTRS | 1984


    Paddle-pin alinement test

    Gilliam, D. M. / Foster, J. A. | NTRS | 1977