We describe a software emulator of the MIL-STD-1750 A architecture that executes 1750A code at a rate of about 4 MIPS on a Sun 200 MHz Ultra2 workstation, and effectively several times faster than that when application-specific optimizations are used. A number of optimization techniques were used, including binary translation and an unusual emulation of the 1750A timers and memory management unit. The performance technologies used within the emulator are for the most part applicable to the emulation of other processor architectures.
High-performance software emulation of 1750 A processor
1997-01-01
552999 byte
Conference paper
Electronic Resource
English
High-Performance Software Emulation of 1750A Processor
British Library Conference Proceedings | 1997
|Emulation of the processor for the distributed processor/memory system
Tema Archive | 1977
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