With increasing computational demands in the defense, science, and commercial sectors, future space missions will require new high-performance computer architectures. Extensive research, benchmarking, and analysis of new and emerging architectures is required to identify and evaluate mappings of space apps on the architectures. In this research, we develop and employ hardware testbeds to emulate and predict performance of the High-Performance Spaceflight Computing (HPSC) processor. This new processor, sponsored by AFRL and NASA, is being developed by Boeing for future space missions. Boeing was chosen because of their proposed “chiplct” design. Each chiplet will feature two quad-core ARM Cortex-A53 CPUs connected by an Advanced Microcontroller Bus Architecture (AMBA). These chiplets can be connected by different serial interfaces which provides the Air Force Research Lab (AFRL) and NASA with a flexible platform to serve a variety of potential mission needs. Two hardware testbeds are used herein to emulate and conduct studies on HPSC. The first is an octa-core ARM Cortex-A53 device consisting of two quad-core processors connected by AMBA. This platform emulates a single HPSC chiplet. The second testbed consists of two quad-core ARM Cortex-A53 processors connected by Gigabit Ethernet (GbE). This platform provides insight into how two chiplets might perform applications together. Using kernel and Ethernet performance results from both platforms, we create a model to project the performance of the HPSC processor across a suite of space-related benchmarks. We project that synthetic aperture radar (SAR), the most compute-intensive application in the suite, will scale well on a multi-chiplet platform. When using two connected chiplets, SAR is forecasted to have a speedup of 1.93 versus a single chiplet. Smaller kernels, such as matrix addition, suffer from significant parallelization overhead across multiple chiplets and even across AMBA on a single chiplet. This slowdown is due to the communication overhead on Ethernet and AMBA, contributing a major part of the total runtime. Additionally, this research uncovered a performance optimization for the 2D-FFT kernel within the popular FFTW library. This optimization led to an average speedup of 1.44 for larger FFT sizes. Overall, the work presented in this paper forecasts and evaluates the benchmarking performance of the HPSC processor for a variety of space-related kernels and reveals techniques to optimize apps for this system.


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    Title :

    Emulation-Based Performance Studies on the HPSC Space Processor


    Contributors:


    Publication date :

    2019-03-01


    Size :

    2998109 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English