Heavy-ion test results utilizing novel test methodologies of non-volatile antifuse-based FPGAs are presented and discussed. In particular, the programmable architectures in the RTAX-S FPGA-family including the I/O structures, and the FPGA core were tested and their cross-sections measured. Previously available SET mitigation solution based on SET filtering was implemented on the RTAX-S test designs and their efficacy proven to reduce the saturation cross-section and increase the LET threshold of the mitigated test designs.


    Access

    Check access

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    SET characterization and mitigation in RTAX-S antifuse FPGAs


    Contributors:


    Publication date :

    2009-03-01


    Size :

    883991 byte





    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



    ASIC versus antifuse FPGA reliability

    McCollum, John | IEEE | 2009


    SEU mitigation for reconfigurable FPGAs

    Czajkowski, D.R. / Samudrala, P.K. / Pagey, M.P. | IEEE | 2006


    Single event mitigation for Xilinx 7-series FPGAs

    Bates, T. / Bridges, C. P. | IEEE | 2018


    SEU mitigation testing of Xilinx Virtex II FPGAs

    Yui, Candice / Swift, Gary / Carmichael, Carl et al. | NTRS | 2003


    Single Event Effects (SEE) Mitigation of Reconfigurable FPGAs

    Czajkowski, D. / Pagey, M. / Goksel, M. et al. | British Library Conference Proceedings | 2006