This paper outlines a VHDL-based modeling methodology targeted towards the class of bus functional models that are described by a comprehensive specification. It discusses the basic modeling approach of a specific specification model, a Futurebus+ system model. In addition, the behavioral design of a portion of the system model is illustrated.<>


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    Title :

    An illustration of specification modeling with VHDL using a Futurebus+ model


    Contributors:
    Izzo, P.A. (author)


    Publication date :

    1994-01-01


    Size :

    458637 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



    An Illustration of Specification Modeling with VHDL Using a Futurebus - Model

    Izzo, P. / IEEE / AIAA | British Library Conference Proceedings | 1994



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