This paper outlines a VHDL-based modeling methodology targeted towards the class of bus functional models that are described by a comprehensive specification. It discusses the basic modeling approach of a specific specification model, a Futurebus+ system model. In addition, the behavioral design of a portion of the system model is illustrated.<>
An illustration of specification modeling with VHDL using a Futurebus+ model
1994-01-01
458637 byte
Conference paper
Electronic Resource
English
An Illustration of Specification Modeling with VHDL Using a Futurebus - Model
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