This paper outlines a VHDL-based modeling methodology targeted towards the class of bus functional models that are described by a comprehensive specification. It discusses the basic modeling approach of a specific specification model, a Futurebus+ system model. In addition, the behavioral design of a portion of the system model is illustrated.<>


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    Titel :

    An illustration of specification modeling with VHDL using a Futurebus+ model


    Beteiligte:
    Izzo, P.A. (Autor:in)


    Erscheinungsdatum :

    01.01.1994


    Format / Umfang :

    458637 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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