High density (HDI) electrical interconnections and vertical optoelectronic interconnections (OE) through-Si links for 3D computational systems have been modeled, and compared and contrasted in the areas of latency, size, and power dissipation. Based upon STA Roadmap projections, which indicate interconnection as a challenge area for coming generations of electronics, optoelectronics may serve a role in chip to chip interconnections for massively parallel computational systems.


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    Title :

    A comparison of CMOS chip to chip interconnections: vertical optical through-Si links versus high density electrical interconnect


    Contributors:
    Brooke, M. (author) / Jokerst, N.K. (author) / Bond, S.W. (author) / Wills, D.S. (author)


    Publication date :

    1998-01-01


    Size :

    310466 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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