With advancement of technology, as electronics industry moves towards a deep submicron region of operation of transistor, there arises a serious problem of subthreshold leakage current which leads the circuit toward power dissipation and propagation delay. Constant aggressive scaling of CMOS is no more beneficial for VLSI industry because it causing various short channel effects as CMOS transistor scaled down below the 16nm. To eliminate these drawback of CMOS, researcher innovate a FinFET device which can improve the performance of circuit with minimum power dissipation in deep sub micron region. In this paper, we are designing and simulating various circuits using FinFET with the help of ASAP7 PDK and cadence virtuoso tool. We analyzed various basic inverter circuits and AOI circuits with their performance parameter like power dissipation and propagation delay. The simulation results illustrate that design of logic circuit using FinFET are more efficient than CMOS devices. In this paper we observe that AOI circuit using domino technique provides 56.88% and 79.59% less power dissipation as compare to sleep NMOS and LECTOR techniques respectively.


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    Title :

    Design of low power AOI FinFET circuits at 7nm


    Contributors:
    Kajal (author) / Sharma, Vijay Kumar (author)


    Publication date :

    2020-11-05


    Size :

    535349 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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