• With cache partitioning & memory pools • Bound WCET behavior much more tightly with ACET behavior. • Minimize “budgeted-but-unused” time. • Enable much higher levels of processor utilization. • Simplify interference pattern analysis in single-core and multicore environments. • Simplify verification & certification processes.


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    Title :

    Managing cache partitioning in multicore processors for certifiable, safety-critical avionics software applications


    Contributors:
    King, Tim (author)


    Publication date :

    2014-10-01


    Size :

    4409971 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English