• With cache partitioning & memory pools • Bound WCET behavior much more tightly with ACET behavior. • Minimize “budgeted-but-unused” time. • Enable much higher levels of processor utilization. • Simplify interference pattern analysis in single-core and multicore environments. • Simplify verification & certification processes.
Managing cache partitioning in multicore processors for certifiable, safety-critical avionics software applications
2014-10-01
4409971 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
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