A new systolic implementation is proposed for multiplication of two n-bit binary numbers. It greatly saves the array size compared to previous solutions, while the throughput is only slightly decreased. Therefore it is very suitable for VLSI array processors. The entire structure is connected in a pipeline.<>


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    Title :

    Systolic array for binary multiplier


    Contributors:
    Wang, L. (author) / Hartimo, I. (author)


    Publication date :

    1994-01-01


    Size :

    181769 byte




    Type of media :

    Conference paper


    Type of material :

    Electronic Resource


    Language :

    English



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