A new systolic implementation is proposed for multiplication of two n-bit binary numbers. It greatly saves the array size compared to previous solutions, while the throughput is only slightly decreased. Therefore it is very suitable for VLSI array processors. The entire structure is connected in a pipeline.<>
Systolic array for binary multiplier
1994-01-01
181769 byte
Conference paper
Electronic Resource
English
Systolic Array for Binary Multiplier
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