A new systolic implementation is proposed for multiplication of two n-bit binary numbers. It greatly saves the array size compared to previous solutions, while the throughput is only slightly decreased. Therefore it is very suitable for VLSI array processors. The entire structure is connected in a pipeline.<>


    Zugriff

    Zugriff prüfen

    Verfügbarkeit in meiner Bibliothek prüfen

    Bestellung bei Subito €


    Exportieren, teilen und zitieren



    Titel :

    Systolic array for binary multiplier


    Beteiligte:
    Wang, L. (Autor:in) / Hartimo, I. (Autor:in)


    Erscheinungsdatum :

    01.01.1994


    Format / Umfang :

    181769 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



    Systolic Array for Binary Multiplier

    Wang, L. / Hartimo, I. / IEEE; Hong Kong Chapter of Signal Processing | British Library Conference Proceedings | 1994


    Design of a Linear Systolic Modular Multiplier/Squarer for the Fast Modular Exponentiation

    Lee, K.-J. / Kim, K.-W. / Lee, W.-H. et al. | British Library Online Contents | 2003


    Systolic Processor Array For Recognition Of Spectra

    Chow, Edward T. / Peterson, John C. | NTRS | 1995


    A Cubic Systolic Array and its Properties

    Ishihara, M. / Tanaka, M. / Kuriyama, K. | British Library Online Contents | 2008