A new systolic implementation is proposed for multiplication of two n-bit binary numbers. It greatly saves the array size compared to previous solutions, while the throughput is only slightly decreased. Therefore it is very suitable for VLSI array processors. The entire structure is connected in a pipeline.<>
Systolic array for binary multiplier
01.01.1994
181769 byte
Aufsatz (Konferenz)
Elektronische Ressource
Englisch
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