Design of a Linear Systolic Modular Multiplier/Squarer for the Fast Modular Exponentiation
INTERNATIONAL JOURNAL OF COMPUTERS AND THEIR APPLICATIONS ; 10 , 1 ; 34-42
01.01.2003
9 pages
Aufsatz (Zeitschrift)
Englisch
DDC: | 004 |
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Effcient Parallel Finite Field Modular Multiplier
British Library Conference Proceedings | 2003
|Efficient parallel finite field modular multiplier
IEEE | 2003
|Systolic Array for Binary Multiplier
British Library Conference Proceedings | 1994
|The Modular Systolic Designs for 2-D IIR Digital Filters
British Library Conference Proceedings | 1992
|SQAC Using Folding-Merging Based Squarer
IEEE | 2019
|