High-level design for low power is difficult to accomplish especially for FPGA designs. Presents a design technique that uses pre-computed tables that characterize the RTL and Intellectual Property (IF) components to estimate power. Actual tables were computed and the low-power design technique demonstrated. The results show that a lower power design can be achieved given this design methodology.
High-level low power FPGA design methodology
2000-01-01
481236 byte
Conference paper
Electronic Resource
English
High-Level Low Power FPGA Design Methodology
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