High-level design for low power is difficult to accomplish especially for FPGA designs. Presents a design technique that uses pre-computed tables that characterize the RTL and Intellectual Property (IF) components to estimate power. Actual tables were computed and the low-power design technique demonstrated. The results show that a lower power design can be achieved given this design methodology.


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    Titel :

    High-level low power FPGA design methodology


    Beteiligte:
    Wolff, F.G. (Autor:in) / Knieser, M.J. (Autor:in) / Weyer, D.J. (Autor:in) / Papachristou, C.A. (Autor:in)


    Erscheinungsdatum :

    01.01.2000


    Format / Umfang :

    481236 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch



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