In this paper, we present an approach to model simulation systems at the Register-Transistor Level RTL for an efficient implementation on Field Programmable Gate Arrays FPGAs. The process uses a hybrid technique utilizing two commercially available tools, Simulink Coder and Xilinx Vivado HLD, as well as a middleware procedure to produce an accurate implementation of a model system in HDL, e.g. Verilog and VHDL. The implementation technique does not require expertise knowledge in Digital Design or Hardware Description Language HDL, yet it produces a complete description of the simulator in HDL. Using an example model of electric ship power system, we evaluate the effectiveness of the approach in developing a precise model in RTL for Real-Time simulation while accelerating the overall execution time.


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    Titel :

    Real-Time FPGA Simulation of Electric Ship Power System Using High-Level Synthesis


    Beteiligte:
    Mustafa, Hadil (Autor:in) / Kredo, Kurtis (Autor:in) / Crosbie, Roy (Autor:in) / Bednar, Richard (Autor:in) / Alavi, Zahrasadat (Autor:in)


    Erscheinungsdatum :

    01.08.2019


    Format / Umfang :

    1170513 byte




    Medientyp :

    Aufsatz (Konferenz)


    Format :

    Elektronische Ressource


    Sprache :

    Englisch




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