This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/execute decoupling and simultaneous multithreading. We investigate how both techniques complement each other: while decoupling features an excellent memory latency hiding efficiency, multithreading supplies the in-order issue stage with enough ILP to hide the functional unit latencies. Its partitioned layout, together with its in-order issue policy makes it potentially less complex, in terms of critical path delays, than a centralized out-of-order design, to support future growths in issue-width and clock speed. The simulations show that by adding decoupling to a multithreaded architecture, its miss latency tolerance is sharply increased and in addition, it needs fewer threads to achieve maximum throughput, especially for a large miss latency. Fewer threads result in a hardware complexity reduction and lower demands on the memory system, which becomes a critical resource for large miss latencies, since bandwidth may become a bottleneck. ; Peer Reviewed ; Postprint (published version)
The synergy of multithreading and access/execute decoupling
1999-01-01
Miscellaneous
Electronic Resource
English
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors , Virtual computer systems , Parallel processing (Electronic computers) , Parallel architectures , Multi-threading , Virtual machines , Processor scheduling , Delays , Sistemes virtuals (Informàtica) , Processament en paral·lel (Ordinadors)
DDC: | 629 |
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