Efficient Systolic Architecture for VLSI Realization of 2-D Hartley-Like Transform
International journal of computers and applications ; 35 , 1 ; 22-28
2013-01-01
7 pages
Article (Journal)
English
DDC: | 004.05 |
© Metadata Copyright the British Library Board and other contributors. All rights reserved.
Efficient Systolic Architecture for VLSI Realization of 2-D Hartley-like Transform
British Library Online Contents | 2013
|British Library Online Contents | 2000
|Systolic VLSI Reed-Solomon Decoder
NTRS | 1986
|British Library Online Contents | 2000
|Hartley Transform in Compression of Medical Ultrasonic Images
British Library Conference Proceedings | 1999
|