Concept for determining susceptibility of integrated circuits to single-event upsets (SEU's) based on direct measurement of critical charge causing upset. Test circuit is modified version of standard complementary metal-oxide/semiconductor static cell. Contains six transistors, connected to form latch that retains state of cell set by input pulses. Makes possible to evaluate vulnerability to SEU during design and development of digital equipment.


    Zugriff

    Zugriff über TIB

    Verfügbarkeit in meiner Bibliothek prüfen


    Exportieren, teilen und zitieren



    Titel :

    Measuring Critical Charges For Single-Event Upsets


    Beteiligte:

    Erschienen in:

    Erscheinungsdatum :

    1988-11-01



    Medientyp :

    Sonstige


    Format :

    Keine Angabe


    Sprache :

    Englisch




    Single event upsets in space

    PETERSEN, E. | AIAA | 1983


    Anomalies due to single event upsets

    ROBINSON, JR., P. / LEE, W. / AGUERO, R. et al. | AIAA | 1990


    New Mode For Single-Event Upsets

    Zoutendyk, John A. / Smith, Lawrence S. / Soli, George A. et al. | NTRS | 1988



    Estimating Rates Of Single-Event Upsets

    Zoutendyk, John A. | NTRS | 1988