Concept for determining susceptibility of integrated circuits to single-event upsets (SEU's) based on direct measurement of critical charge causing upset. Test circuit is modified version of standard complementary metal-oxide/semiconductor static cell. Contains six transistors, connected to form latch that retains state of cell set by input pulses. Makes possible to evaluate vulnerability to SEU during design and development of digital equipment.
Measuring Critical Charges For Single-Event Upsets
NASA Tech Briefs ; 12 , 10
1988-11-01
Miscellaneous
No indication
English
AIAA | 1983
|Anomalies due to single event upsets
AIAA | 1990
|System effects of single event upsets
AIAA | 1989
|Estimating Rates Of Single-Event Upsets
NTRS | 1988
|Anomalies due to Single Event Upsets
Online Contents | 1994
|