Concept for determining susceptibility of integrated circuits to single-event upsets (SEU's) based on direct measurement of critical charge causing upset. Test circuit is modified version of standard complementary metal-oxide/semiconductor static cell. Contains six transistors, connected to form latch that retains state of cell set by input pulses. Makes possible to evaluate vulnerability to SEU during design and development of digital equipment.


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    Title :

    Measuring Critical Charges For Single-Event Upsets


    Contributors:

    Published in:

    Publication date :

    1988-11-01



    Type of media :

    Miscellaneous


    Type of material :

    No indication


    Language :

    English




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