The author describes the design of a MIL-STD-1750A mission processor (MP), which is generally based on the US Air Force Pave Pillar architecture. The MP is composed of a power conditioner unit, a chassis assembly, and a set of SEM-E (3/4 ATR)-size common modules. The common modules utilize a set of seven complex submicrometer CMOS integrated circuits as building blocks. The internal design architecture features a dual PI-Bus for intermodule communication and a dual TM-Bus for operational test and maintenance. The MP is capable of over 22-million-instruction/s performance on the Defense Avionics Instructions Set (DAIS) mix and contains up to 2.56 million words of random-access memory and 288 thousand words of read-only memory. The MP provides external interfaces to three dual redundant MIL-STD-1553B serial communication buses, two differential Small Computer System Interface (SCSI) buses, and IEEE-488 bus, and miscellaneous digital and analog discrete lines.
Submicron CMOS MIL-STD-1750A based mission processor
Ein Prozessor nach MIL-STD-1750A in CMOS-Technik
1989
4 Seiten
Conference paper
English
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