VLSI/VHSIC technology poses critical test problems not only at the device level, but also at the system level. The extreme functional complexity and fail-operational redundancy of VLSI systems tends to render conventional performance testing inadequate, not only in terms of failure mode coverage, but also in terms of test-time requirements. The authors propose a design structure in which various subsystems and modules using VLSI devices are related to one another in a hierarchical test scheme based on the reporting of individual, device-level built-in-test (BIT) results. This hierarchical approach offers true consistency between operational (in-flight), organizational, and depot-level test methodologies.


    Access

    Check access

    Check availability in my library

    Order at Subito €


    Export, share and cite



    Title :

    Hierarchical testing of VLSI systems based on device BIT


    Additional title:

    Hierarchische Pruefung von VLSI-Systemen mit eingebauten Pruefeinrichtungen


    Contributors:


    Publication date :

    1988


    Size :

    8 Seiten, 3 Quellen



    Type of media :

    Conference paper


    Type of material :

    Print


    Language :

    English




    VLSI Hierarchical Placement Using Discrete Tunneling Algorithm

    Koakutsu, S. / Nagano, H. / Hirata, H. | British Library Online Contents | 1995



    Constructing VLSI gas distribution systems

    Lyon, R.C. | Tema Archive | 1988


    VLSI/VHSI device technology

    Buss, D.D. | Tema Archive | 1979


    Pin-Type Based VLSI Partitioning

    Uygur, Gürkan / Sattler, Sebastian M. | VDE-Verlag | 2014