Field Programmable Gate Arrays (FPGAs) are being used in space applications because of attractive attributes: good density, moderate speed, low cost, and quick turn-around time. However, these devices are susceptible to Single Event Upsets (SEUs). An approach using triple modular redundancy (TMR) and feedback was developed for flip-flop hardening in these devices. Test data showed excellent results for this circuit topology. Total dose and Single Event Effect (SEE) testing have been performed on recently released technologies. Failures are analyzed and test methodology is discussed.


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    Title :

    SEU hardening of field programmable gate arrays (FPGAS) for space applications and device characterization


    Additional title:

    Sogenannte SEU (single event upset)-Festigkeit auf feldprogrammierbaren Gate-Arrays für Anwendungen in der Raumfahrt und Gerätecharakterisierung


    Contributors:
    Katz, R. (author) / Barto, R. (author) / McKerracher, P. (author) / Koga, P. (author)


    Publication date :

    1994


    Size :

    8 Seiten, 4 Bilder, 5 Tabellen, 6 Quellen




    Type of media :

    Conference paper


    Type of material :

    Print


    Language :

    English




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