A high-voltage CMOS technology featuring a 45 V maximum blocking voltage is described. The transistor output characteristics at high voltages are simulated by employing an impact-ionisation current model and the results are verified by measurements on fabricated test structures. Paper inverter operation is maintained up to a supply voltage of 35 V, despite a large impact-ionisation-induced mismatch in the pMOS and nMOS output characteristics at high voltages. In addition, simulation results reveal that impact-ionisation currents have little effect on inverter performance in terms of power dissipation. The inverter delay times are also found to be independent of the transistor sizes for supply voltages of above 25 V; therefore, small-geometry transistors can be used to reduce the overall area of the high-voltage circuits.


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    Title :

    Theoretical and experimental evaluation of high-voltage CMOS inverters


    Additional title:

    Theoretische und experimentelle Entwicklung von Hochspannungs-CMOS-Invertern


    Contributors:

    Published in:

    Publication date :

    1994


    Size :

    5 Seiten, 9 Bilder, 2 Tabellen, 10 Quellen




    Type of media :

    Article (Journal)


    Type of material :

    Print


    Language :

    English




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